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Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B520F2048IQ64 /CMU /LFAPRESC0

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Interpret as LFAPRESC0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIV1)LETIMER0 0 (DIV1)LETIMER1 0 (DIV1)LESENSE 0 (DIV1)LCD0 (DIV1)RTC

LETIMER1=DIV1, LCD=DIV1, LETIMER0=DIV1, RTC=DIV1, LESENSE=DIV1

Description

Low Frequency a Prescaler Register 0 (Async Reg)

Fields

LETIMER0

Low Energy Timer 0 Prescaler

0 (DIV1): LFACLKLETIMER0 = LFACLK

1 (DIV2): LFACLKLETIMER0 = LFACLK/2

2 (DIV4): LFACLKLETIMER0 = LFACLK/4

3 (DIV8): LFACLKLETIMER0 = LFACLK/8

4 (DIV16): LFACLKLETIMER0 = LFACLK/16

5 (DIV32): LFACLKLETIMER0 = LFACLK/32

6 (DIV64): LFACLKLETIMER0 = LFACLK/64

7 (DIV128): LFACLKLETIMER0 = LFACLK/128

8 (DIV256): LFACLKLETIMER0 = LFACLK/256

9 (DIV512): LFACLKLETIMER0 = LFACLK/512

10 (DIV1024): LFACLKLETIMER0 = LFACLK/1024

11 (DIV2048): LFACLKLETIMER0 = LFACLK/2048

12 (DIV4096): LFACLKLETIMER0 = LFACLK/4096

13 (DIV8192): LFACLKLETIMER0 = LFACLK/8192

14 (DIV16384): LFACLKLETIMER0 = LFACLK/16384

15 (DIV32768): LFACLKLETIMER0 = LFACLK/32768
LETIMER1

Low Energy Timer 1 Prescaler

0 (DIV1): LFACLKLETIMER1 = LFACLK

1 (DIV2): LFACLKLETIMER1 = LFACLK/2

2 (DIV4): LFACLKLETIMER1 = LFACLK/4

3 (DIV8): LFACLKLETIMER1 = LFACLK/8

4 (DIV16): LFACLKLETIMER1 = LFACLK/16

5 (DIV32): LFACLKLETIMER1 = LFACLK/32

6 (DIV64): LFACLKLETIMER1 = LFACLK/64

7 (DIV128): LFACLKLETIMER1 = LFACLK/128

8 (DIV256): LFACLKLETIMER1 = LFACLK/256

9 (DIV512): LFACLKLETIMER1 = LFACLK/512

10 (DIV1024): LFACLKLETIMER1 = LFACLK/1024

11 (DIV2048): LFACLKLETIMER1 = LFACLK/2048

12 (DIV4096): LFACLKLETIMER1 = LFACLK/4096

13 (DIV8192): LFACLKLETIMER1 = LFACLK/8192

14 (DIV16384): LFACLKLETIMER1 = LFACLK/16384

15 (DIV32768): LFACLKLETIMER1 = LFACLK/32768
LESENSE

Low Energy Sensor Interface Prescaler

0 (DIV1): LFACLKLESENSE = LFACLK

1 (DIV2): LFACLKLESENSE = LFACLK/2

2 (DIV4): LFACLKLESENSE = LFACLK/4

3 (DIV8): LFACLKLESENSE = LFACLK/8
LCD

Liquid Crystal Display Controller Prescaler

0 (DIV1): LFACLKLCD = LFACLK

1 (DIV2): LFACLKLCD = LFACLK/2

2 (DIV4): LFACLKLCD = LFACLK/4

3 (DIV8): LFACLKLCD = LFACLK/8

4 (DIV16): LFACLKLCD = LFACLK/16

5 (DIV32): LFACLKLCD = LFACLK/32

6 (DIV64): LFACLKLCD = LFACLK/64

7 (DIV128): LFACLKLCD = LFACLK/128
RTC

Real-Time Counter Prescaler

0 (DIV1): LFACLKRTC = LFACLK

1 (DIV2): LFACLKRTC = LFACLK/2

2 (DIV4): LFACLKRTC = LFACLK/4

3 (DIV8): LFACLKRTC = LFACLK/8

4 (DIV16): LFACLKRTC = LFACLK/16

5 (DIV32): LFACLKRTC = LFACLK/32

6 (DIV64): LFACLKRTC = LFACLK/64

7 (DIV128): LFACLKRTC = LFACLK/128

8 (DIV256): LFACLKRTC = LFACLK/256

9 (DIV512): LFACLKRTC = LFACLK/512

10 (DIV1024): LFACLKRTC = LFACLK/1024

11 (DIV2048): LFACLKRTC = LFACLK/2048

12 (DIV4096): LFACLKRTC = LFACLK/4096

13 (DIV8192): LFACLKRTC = LFACLK/8192

14 (DIV16384): LFACLKRTC = LFACLK/16384

15 (DIV32768): LFACLKRTC = LFACLK/32768

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data